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Cover Art
Author Meer, P. R.

Title Low-Power Deep Sub-Micron CMOS Logic [electronic resource] : Sub-threshold Current Reduction / by P.R. Meer, A. Staveren, A.H.M. Roermund.

Published Boston, MA : Springer US, 2004.


Location Call No. Status
Physical description 1 online resource (xiv, 154 pages with CD-ROM.).
Series The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing, 0893-3405 ; 841
Kluwer international series in engineering and computer science. Analog circuits and signal processing ; 841.
Contents Index of Symbols -- 1. Introduction -- 2. Power Versus Energy -- 3. Power Dissipation in Digital CMOS Circuits -- 4. Reduction of Functional Power Dissipation -- 5. Reduction of Parasitical Power Dissipation -- 6. Weak-inversion Current Reduction -- 7. Effectiveness of Weak-inversion Current Reductions -- 8. Triple-S Circuit Designs -- 9. Conclusions -- 10. Summary -- References -- Index.
Summary The strong interaction between the demand for increasing chip functionality and data-processing speeds, and technological trends in the integrated circuit industry, like e.g. shrinking device geometry, growing chip area and increased transistor switching speeds, cause a huge increase in power dissipation for deep sub-micron digital CMOS circuits. Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction classifies all power dissipation sources in digital CMOS circuits and provides for a systematic approach of power reduction techniques. A clear distinction has been made between power dissipated to perform a calculation in a certain time frame, i.e. functional power dissipation, and power dissipated even when a circuit is idle, i.e. parasitical power dissipation. The threshold voltage level forms an important link between the functional and the parasitical power dissipation. Since for high data-processing speeds the threshold voltage needs to be low, whereas for low sub-threshold leakage currents it needs to be high. The latter is extremely important for battery operated circuits in standby modes. Therefore, a separate classification of sub-threshold current reduction techniques is presented showing existing and new circuit topologies. Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction is a valuable book for researchers, designers as well as students in the field of low-power digital design. Power dissipation is discussed from a fundamental, quantum mechanical and a practical point of view. Theory is accompanied with practical circuit implementations and measurement results.
Other author Staveren, A.
Roermund, A. H. M.
Subject Engineering.
Engineering design.
Computer engineering.
Electronic books.
ISBN 9781402028496 (electronic bk.)
1402028490 (electronic bk.)