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SUBJECTS (1-16 of 16)
Computer hardware description languages.
1
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    E-RESOURCE 2002

Architecture exploration for embedded processors with LISA / by Andreas Hoffmann, Heinrich Meyr, and Rainer Leupers.

    Hoffmann, Andreas.
Boston : Kluwer Academic Publishers,        1 online resource (viii, 230 pages) : illustrations 2002
2
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    E-RESOURCE c2010

C compilers for ASIPs automatic compiler generation with LISA / [electronic resource] : Manuel Hohenauer, Rainer Leupers.

    Hohenauer, Manuel.
New York : Springer,        1 online resource (xv, 223 p.) : ill. c2010
3
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    E-RESOURCE c2010

Debugging at the electronic system level / [electronic resource] / Frank Rogin, Rolf Drechsler.

    Rogin, Frank.
Dordrecht ; New York : Springer,        xix, 199 p. c2010
4
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    PRINTED BOOKS 2004

The E hardware verification language / Sasan Iman, Sunita Joshi.

    Iman, Sasan.
Boston : Kluwer Academic Publishers,        xxii, 348 pages : illustrations ; 24 cm 2004
5
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    E-RESOURCE  

The E hardware verification language / [electronic resource] / Sasan Iman, Sunita Joshi.

    Iman, Sasan.
Boston : Kluwer Academic Publishers,        1 online resource (xv, 349 pages) : illustrations  
6
Cover Art
    E-RESOURCE c2008

High-level synthesis from algorithm to digital circuit / [electronic resource] : Philippe Coussy, Adam Morawiec, editors.

   
[New York] : Springer,        1 online resource (xv, 297 p.) : ill. c2008
7
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    PRINTED BOOKS 2004

Higher level hardware synthesis / Richard Sharp.

    Sharp, Richard (Richard William), 1978-
Berlin ; New York : Springer-Verlag,        pages cm. 2004
8
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    E-RESOURCE 2004

Higher-level hardware synthesis / Richard Sharp.

    Sharp, Richard (Richard William), 1978-
Berlin ; New York : Springer,        1 online resource (xvi, 195 pages) : illustrations. 2004
9
Cover Art
    E-RESOURCE 2004

Higher-level hardware synthesis / Richard Sharp.

    Sharp, Richard (Richard William), 1978-
Berlin ; New York : Springer,        xvi, 195 pages : illustrations ; 24 cm. 2004
10
Cover Art
    E-RESOURCE c2001

Hybrid parallel execution model for logic-based specification languages / [electronic resource] / Jeffrey J.P. Tsai, Bing Li.

    Tsai, Jeffrey J.-P.
Singapore ; New Jersey : World Scientific,        xii, 214 p. : ill. c2001
11
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    E-RESOURCE 2019

Introduction to digital systems design / Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita.

    Donzellini, Giuliano, author.
Cham, Switzerland : Springer,        1 online resource (xxiii, 536 pages) : illustrations (some color). 2019
12
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    E-RESOURCE 2006

Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton.

    Reese, Robert B. (Robert Bryan), 1958-
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers,    1st ed.    1 electronic text (vii, 75 pages : illustrations) : digital file. 2006
13
Cover Art
    E-RESOURCE c2007

Optimized ASIP synthesis from architecture description language models / [electronic resource] / Oliver Schliebusch, Heinrich Meyr, Rainer Leupers.

    Schliebusch, Oliver.
Dordrecht ; London : Springer,        1 online resource (xiv, 193 p.) : ill. c2007
14
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    E-RESOURCE c2012

SystemVerilog for verification a guide to learning the testbench language features / [electronic resource] : Chris Spear, Greg Tumbush.

    Spear, Chris.
New York : Springer,    3rd ed.    1 online resource (xliii, 464 p.) c2012
15
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    E-RESOURCE  

Writing testbenches functional verification of HDL models / [electronic resource] : Janick Bergeron.

    Bergeron, Janick.
Boston : Kluwer Academic,        1 online resource (xxii, 354 pages) : illustrations  
16
Cover Art
    PRINTED BOOKS c2006

Writing testbenches using SystemVerilog / by Janick Bergeron.

    Bergeron, Janick.
New York : Springer,        xxvi, 412 p. : ill. ; 25 cm. c2006
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