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Cover Art
Author Noia, Brandon, author.

Title Design-for-test and test optimization techniques for TSV-based 3D stacked ICs / Brandon Noia, Krishnendu Chakrabarty ; foreword by Vishwani Agrawal.

Published Cham : Springer, 2014.


Location Call No. Status
Physical description 1 online resource (xviii, 247 pages) : illustrations (some color)
Contents Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.
Summary This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
Notes Description based on online resource; title from PDF title page (SpringerLink, viewed November 18, 2013).
Other author Chakrabarty, Krishnendu, author.
Agrawal, Vishwani D., 1943-, writer of supplementary textual content.
Subject Three-dimensional integrated circuits -- Testing.
Three-dimensional integrated circuits -- Design and construction.
Electronic books.
ISBN 9783319023786 (electronic bk.)
3319023780 (electronic bk.)
Standard Number 10.1007/978-3-319-02378-6