| Physical description |
1 online resource (viii, 270 pages) : illustrations |
| Bibliography |
Includes bibliographical references and index. |
| Contents |
Multiprocessor System-on-Chip; Preface; Contents; Chapter 1: An Introduction to Multi-Core System on Chip -- Trends and Challenges; 1.1 From SoC to MPSoC; 1.2 General Structure of MPSoC; 1.3 Power Efficiency and Adaptability; 1.4 Complexity and Scalability; 1.5 Heterogeneous and Homogeneous Approaches; 1.6 Multi variable Optimization; 1.7 Static vs Dynamic Centralized and Distributed Approaches; 1.8 Conclusion; References; Part I: ``Application Mapping and Communication Infrastructure ́ ́ |
|
Chapter 2: Composability and Predictability for Independent Application Development, Verification, and ExecutionChapter 3: Hardware Support for Efficient Resource Utilization in Manycore Processor Systems; Chapter 4: PALLAS: Mapping Applications onto Manycore; Chapter 5: The Case for Message Passing on Many-Core Chips; Part II: ``Reconfigurable Hardware in Multiprocessor Systems ́ ́; Chapter 6: Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support; Part III: ``Physical Design of Multiprocessor Systems ́ ́ |
|
Chapter 7: Design Tools and Methods for Chip Physical DesignChapter 8: Power-Aware Multicore SoC and NoC Design; Part IV: Trends and Challenges for Multiprocessor Systems; Chapter 9: Embedded Multicore Systems: Design Challenges and Opportunities; Chapter 10: High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market; Chapter 11: Invasive Computing: An Overview; Index. |
| Summary |
Improving future electronic system performance can only be achieved by exploiting parallelism on all system levels. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promises extreme computing power for highly CPU-time-consuming applications. FPGA-based accelerators not only offer the opportunity to speed up an application by implementing their compute-intensive kernels into hardware, but also to adapt to the dynamical behavior of an application. This book describes strategies for future system design in multiprocessor system-on-chip (MPSoC) architectures. Both hardware design and integration of new development tools are discussed. Novel trends in MPSoC design, combined with reconfigurable architectures are a main topic of concern. The main emphasis is on architectures, design-flow, tool-development, applications and system design. This book deals with key issues such as on-chip communication architectures, integration of reconfigurable hardware, and physical design of multiprocessor systems.-Provides a state-of-the-art overview of system design using MPSoC architectures; -Describes current trends in on-chip communication architectures; -Offers extensive coverage of system design integrating MPSoC architectures with reconfigurable hardware; -Includes coverage of challenges in physical design for multi- and manycore hardware architectures. |
| Notes |
Springer eBooks |
| Other author |
Hübner, Michael, 1970-
|
|
Becker, Jürgen.
|
| Subject |
Multiprocessors.
|
|
Multiprocessors -- Design and construction.
|
|
Systems on a chip -- Design and construction.
|
| ISBN |
9781441964601 (electronic bk.) |
|
1441964606 (electronic bk.) |
|
1441964592 (electronic bk.) |
|
9781441964595 (electronic bk.) |
| Standard Number |
10.1007/978-1-4419-6460-1 |
|
